Desktop Application for Network-on-Chip (NoC) Design

Features a graphic user interface (GUI) with drag and drop capabilities

Arteris IP is a well-known expert in System-on-Chip (SoC) design. It is also the top company for on-chip communication technologies.

Problem

Arteris IP was creating a tool to help with Network-on-Chip (NoC) design in computer chips.

Softeq provided a dedicated team to help improve the tool’s features and user experience (UX). We also helped to deliver the desktop version of the application.

Solution

Arteris IP is developing Maestro Unix Desktop Software—a brand new product aimed to apply graphical user interface (GUI) tools and drag and drop methods to NoC design.

The end goal is to configure the optimal placement of on-chip components and consequently deliver chips with improved interconnect timing between IP blocks.

While the platform application is primarily built with C++, for the desktop part of the app we chose Tcl as the user’s default coding language for electronic design. Our team quickly managed to speed up GUI development and leverage the Tcl’s dynamic approach and compact code.

As a result, we have delivered a desktop application which:

Provides a GUI interface to define custom chip interconnect design
Automates the design completion processes
Ensures design consistency
Enables intuitive navigation through a design flow
Supports a Tcl-based interface and Tcl scripts
Helps prepare a chip floor plan design specification

Challenges

Legacy Code Base

When we started working with the client, the project had been going on for several years already and the code needed refactoring to expand the application's functionality and improve its performance. Our engineers performed a continuous analysis of the existing code base, highlighted the parts to be improved or redone, and updated the system.

Processes

Managing dispersed teams is never easy, so our team ensured transparent processes on our side by tracking activities in Jira and organizing regular meetings with the client.

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Result

The roadmap for the current solution projects at least four years into the future and Arteris is planning to continue working with our team and broaden the scope of our participation in the project.

We have taken a proactive approach to the project and already see how we can assist the client with further development processes, namely algorithms allowing the client to optimize the location of the design IP components on a chip.